IBIS Macromodel Task Group Meeting date: 25 August 2020 Members (asterisk for those attending): Achronix Semiconductor: * Hansel Dsilva ANSYS: Curtis Clark * Wei-hsing Huang Cadence Design Systems: * Ambrish Varma Ken Willis * Jared James Google: * Zhiping Yang Intel: Michael Mirmak Keysight Technologies: * Fangyi Rao Radek Biernacki Ming Yan Todd Bermensolo Stephen Slater * Rui Yang Marvell: Steve Parker Mentor, A Siemens Business: * Arpad Muranyi Micron Technology: * Randy Wolff * Justin Butterfield SiSoft (Mathworks): * Walter Katz Mike LaBonte Teraspeed Labs: * Bob Ross Zuken USA: Lance Wang The meeting was led by Arpad Muranyi. Justin Butterfield took the minutes. -------------------------------------------------------------------------------- Opens: - Walter would like to discuss the topic of RDL or Redistribution Layer. ------------- Review of ARs: - Ambrish to find out whether his team would have any interest in taking some of their BCI protocols public if there were a process to do so. - Ambrish reported this is being discussed. This is something they may be interested to do, once there is a process to do so. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the August 18 meeting. Randy moved to approve the minutes. Walter seconded the motion. There were no objections. ------------- New Discussion: Redistribution Layer (RDL) Discussion: Randy shared his IBIS Summit presentation from DesignCon 2014. The presentation shows stacked die configurations of memory components. Randy noted one of the cases is a face-to-face stacked package where the power routing uses the bumps between the die. Walter noted the bond bads are on the sides of the die. And, all of the IO buffers are in the center of the chip. The Redistribution Layer routes from the bond pads to the buffers. Randy said this is correct. Walter asked how we represent this in an IBIS model. Arpad asked if we can use the new Interconnect Model to model between the pad and the buffer. Walter replied you could say the RDL is part of the package. Arpad asked if the RDL is part of the package or the die. Walter replied it could be either. Randy agreed. Walter commented the RDL could be different in each layer of the stack. The die are the same, but the routing would have a different model for each component. In this case, it would be nice to have the RDL as part of the package model. Walter asked what happens if you have two wire bond pads on the same signal. We do not allow this in the IBIS Component. We could use EMD, but this would be a lot of overhead. Walter suggested it could be nice to add an RDL pin section that would have all the RDL pins in a separate section. The problem is in the Pin section each pin must have a unique signal_name. In the case of the RDL component, the signal_name could be the same. Arpad asked if this means adding a third section to Component. Walter replied you would have an RDL pin list, where you could have more complicated RDL topologies. His goal is to introduce the idea and see if anyone else has seen the same issue. Arpad asked if we would allow splits and joins in the IBIS Component. Walter replied it would allow two RDL pins to connect to one buffer. Arpad asked if this does away with the one-to-one pin to buffer rule. Walter commented this would allow multiple pins to connect to one buffer but not allow multiple buffers to connect to one pin. A signal_name could be on multiple wire bond pads in this case. Arpad asked if this is something Randy would like to have in the IBIS specification. Randy replied this is a different case from what he usually sees, where he has one pin that connects to more than one buffer. Arpad asked if this can be done in the EMD. Walter noted it can be done in the EMD, but it is a large amount of overhead to create the EMD for one specific problem. Randy asked about the Rambus clock example. Walter replied this allows the clock to connect through the package. Bob asked if one buffer can go to multiple pins and if this is all done in the RDL. Walter agreed this is what he is asking for. Walter noted there would not be much to the BIRD. He suggested for people to think about it, and the use cases. Bob commented one idea would be to specify the exceptions. Walter stated one other idea could be to allow the same signal_name to be used in two pin_names. Arpad noted he had proposed this change before the Interconnect specification. Walter commented it could be simple to remove the rule for one-to-one pin to buffers. Bob noted there is nothing that depends on the signal_name, and it is not used for I/O pins. Walter agreed signal_name is not currently used. Walter noted he can simplify the rule as an alternative BIRD. Bob commented we would have to enforce differences in signal_name. Walter stated the same signal_names would be connected, but you don't know the connection. The rule would be that two IO pins may have the same signal_name, and if they have the same signal_name, they must have the same model_name. How they are connected is based on the content of the subcircuit. Randy asked if this would only work with the [Interconnect Model] or with the [Pin] and [Package Model]. Walter replied it would apply to both cases. Bob noted we are allowing to have this at the EMD interface, and this is proposing to do this in the Component. Walter agreed this is correct. Bob stated there was never a technical reason for this restriction. Walter commented this would be relaxing the restriction. Walter will prepare a BIRD to relax the restriction on the one-to-one pin to buffer rule. - Randy: Motion to adjourn. - Walter: Second. - Arpad: Thank you all for joining. AR: Walter to prepare a BIRD to relax the restriction on the one-to-one pin to buffer rule. ------------- Next meeting: 1 September 2020 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives